1. Field of the Invention
The present invention relates to a test system using an extended Joint Test Action Group (JTAG) interface, and more particularly to a test system which is provided on a printed circuit board or a semiconductor chip having a test target system such as a logic circuit and which tests the test target system by circulatively setting or obtaining enable data and input/output data in such a semiconductor chip.
2. Description of the Related Art
A technology, which is referred to as JTAG or Boundary Scan, has been developed in the early 1990's and has been helpful in treating inspection or test-related problems, caused by difficulty in physical access to devices such as multilayer Printed Circuit Boards (PCB), Ball Grid Arrays (BGA), and integrated circuits having a number of pins due to significant evolution of such devices. Currently, this technology is standardized as IEEE1149.1 and is used even for writing to nonvolatile memories on multilayer PCBs or the like.
A serial interface of 4 terminals (with an optional fifth terminal) for accessing complicated integrated circuits or the like is defined in IEEE1149.1. A test system according to IEEE1149.1 is described, for example, in Japanese Patent Application Kokai (Laid-open Application) No. 9-15300 and No. 11-326460. The test systems of these Japanese Patent Application Kokai are referred to as “conventional test system” in the following description.
FIG. 13 of the accompanying drawings is a conceptual diagram illustrating the architecture of a device including an integrated circuit on which such a conventional test system is provided, and FIG. 14 is a schematic diagram illustrating the configuration of a boundary scan circuit on which a plurality of the devices of FIG. 13 is provided.
A device 10 shown in FIG. 13 has an internal core logic circuit 11 which is a test target system. A plurality of data input terminals “IN” and a plurality of data output terminals “OUT” are connected to the internal core logic circuit 11 via an input/output (I/O) bus (not shown). A plurality of boundary scan cells (BSC) for performing boundary scan functions are provided between the internal core logic circuit 11 and the data input terminals “IN” and between the internal core logic circuit 11 and the data output terminals “OUT”. The BSCs 12 are each a 1-bit shift register capable of setting test data, and they are connected in series to form a Boundary Scan Path Chain (BSPC). A Test Access Port (TAP) 13 is provided to control input/output of the BSPC. The TAP 13 includes a bypass register, an Instruction Register (IR), a device identification (ID) register, a TAP control circuit, etc. A state machine for performing the boundary scan function is provided in the TAP control circuit.
Standard serial interface terminals, for example, 5 terminals (i.e., a test data input terminal (TDI), a test data output terminal (TDO), a test clock input terminal (TCK), a test mode selection terminal (TMS), and a test logic reset input terminal (TRST*) are connected to the TAP 13. Data input to the device 10 through the terminal TDI is stored in either the instruction register or the data register in the TAP 13. Data from the device 10 is output through the terminal TDO. The BSPC, composed of a plurality of the BSCs 12, operates according to a test clock supplied through the terminal TCK. The test clock of the terminal TCK is independent of a system clock sck. The system clock sck is used to operate the device 10. The state of the TAP 13 is controlled based on a signal from the terminal TMS. A signal from the terminal TRST* is optional and is used as a hardware reset signal.
The operation of the internal core logic circuit 11 and the operation of the test circuit composed of the BSCs 12 and the TAP 13 are switched according to the signal of the terminal TMS which is synchronized with the test clock of the terminal TCK. Specifically, according to the signal of the terminal TMS, the path of test data in the device 10 (internal scan path) is switched between the path “terminal TDI→BSCs 12→terminal TDO” and the path “terminal TDI→bypass register in TAP 13→terminal TDO”. During test operation, according to the signal of the terminal TMS, the path of test data is the path “terminal TDI→shift registers in BSCs 12→terminal TDO”, and the test data is set in the BSCs 12. Then, the internal core logic circuit 11 is tested based on the test data.
A BSPC, which is a boundary scan chain, can be formed by connecting a plurality of such devices 10 (for example, six devices 10-1 to 10-6) in series on a printed circuit board 20 as shown in FIG. 14. Thus, a “chain” is formed on the printed circuit board 20. Specifically, terminals TDI and TDO of the devices 10-1 to 10-6 are connected in series on the printed circuit board 20, thereby forming a single scan path. Both ends of this scan path are connected to terminals ATDI and ATDO on an edge connector 21 of the printed circuit board 20.
If a JTAG control circuit, which is provided externally to perform boundary scan test, sets test data for testing manufacturing failure of the printed circuit board 20 to a test target device (for example, to a test data setting point P of the device 10-3), the test data is serially input to the device 10-1, which is the first device on the scan path, through the terminal ATDI and the terminal TDI of the device 10-1, and the input test data is output from the device 10-1 through a terminal TDI of the device 10-1 after passing through a bypass register in a TAP 13 thereof. The test data proceeds through a terminal TDI, a bypass register, and a terminal TDO of the device 10-2. Subsequently, the test data is input to the test target device 10-3 through a terminal TDI of the device 10-3 so that the test data is set in the BSCs 12 in the device 10-3. After the test is completed, the test data is output from the test target device 10-3 through a terminal TDO of the device 10-3. The test data passes through bypass circuits of the downstream devices 10-4 and 10-5. The test data is supplied from a terminal TDO of the last device 10-6 to the terminal ATDO of the edge connector 21.
Such a scan operation provides a capability to test a structural failure of the printed circuit board 20 occurring when it is manufactured and a capability to perform in-system programming. This significantly reduces the number of spots of the printed circuit board 20 which need to be tested. The scan operation also makes it possible to directly enjoy advantages such as a simplified layout of the printed circuit board 20, low-cost test equipment, reduced test time, an additional use of a standard interface, and adaptation to the market.
Despite these excellent features, the JTAG has encountered limitations with recent large-scale devices 10 or PCBs.
First, 1-bit serial data transfer requires a device 10 having 100 or more (terminals) pins to have a number of clocks for setting inputs or extracting outputs for test. This imposes a large burden on the external JTAG control circuit which controls the test target device (for example, the device 10-3 in FIG. 14). Also, there are limitations in reducing the test time. The 1-bit serial data transfer also causes a problem in writing to a flash memory or the like using the boundary scan circuit. In the current technology, the flash memory write time is about 1 ms/page (one page is, for example, 512 bytes in size), and the 1-bit serial data must be converted into pages, so that a significant processing load is also imposed on the external JTAG control circuit.
Second, even if multiple bit serial data transfer (for example, a multiple bit test bus) is implemented to solve the above problems, the volume of the test circuitry is increased and the chip cost of the device 10 is increased since the test bus must be wired around all the input/output terminals or pins and the number of test terminals is also increased.